ASIC Verifier
ASIC Verification Engineer
Monday, July 4, 2016
Clock generation in testbench environment
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Clock generation is the key of any design and verification environment. There are many ways to generate clock, some of them are listed bel...
Monday, February 22, 2016
difference between uvm_resource_db & uvm_config_db
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From the usage perspective there is no difference between these two and recommendation is to use uvm_config_db Both uvm_config_db...
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